Alexander Sidokhine

- Originator of split lots to improve or fix device performance. - Analysis of split lots. Originator of Corner lots. - Responsible for driving and successfully accomplishing device reliability topics. - Initiator and active participant in Test program debugging. - Successfully implemented on silicon new EDMOS, DRIFT devices for higher voltages. - Responsible in various milestone activities for devices. - PCRB data analysis for 28nm.

1.Dielectric reliability assessment-package,wafer level - CVS (Constant Voltage Stress); - CSS (Constant Current Stress); 2. Device Reliability: - Beta Degradation of Bipolar transistor and life time of a device; - HCI ( Hot Carrier Injection) degradation and life time prediction for MOS transistor-wafer level - HCI degradation and life time prediction of LDMOS devices (20V,40V,60V devices)-wafer level. 3. Electro Migration tests (package level)

- Analysis of split lots with further recommendation to process modules - Statistical control of parameters at first and final measurement of Electrical parameters - Debugging of measurement structures - Creating and editing of production and engineering test programs - Limit file creation - Verification of results in the lab if needed - Test time reduction - Cp/CpK reports

- FA on the cell level - FA of systematic failures - Sort Flow development - PFA for single cells; - Statistical analysis in case of mass production. - Reliability investigations for example all kinds of disturbs with the Flash Cells.

Owner of several sub-micron Analog and Mixed Signal devices.Monitoring in-line performance through PROMIS.Monitoring ET and Sort results.Conducting investigation in case of ET or Sort failures including FA request and further analysis of FA results, commonality analysis, ET-Sort correlation etc, using all features of Klarity Ace software.Customer support, reporting on current status of lots and results of Yield analysis.Launching new products based on corner lot results.Lab verification of failed ET param.

On-call Sustaining; ET results monitoring for EPROM, Flash Memories, Analog and CMOS Products;Sort results monitoring for EPROM and Flash Memories, Analog and CMOS Products; Statistical Process Control;Identifying major yield killers through end-of-line test and in-line defect detection; Discovering Root Cause for major crashes using Failure Analysis tools and technique: Sort and Test with MOSAID to classify and locate a failure.Process Commonality analysis.Chemical De-Processing.