Matthew Cappello

VHDL code development – Create synthesizable code in both Actel Libero and Xilinx Vivado design environments Timing constraints and closure – Produce Synopsis Design Constraint files to ensure proper timing closure for internal and external interface signals Documentation – Author documentation for FPGA firmware including interface guides and functional diagrams; use DOORS to capture requirements Interdisciplinary work – Collaborate closely with software and hardware engineers in an Agile environment

VHDL code development–Created synthesizable code in Libero and Quartus II Timing constraints/closure–Produced SDC files to ensure proper timing closure Documentation–Authored documentation for FPGA firmware Digital/Analog Design–Hardware development with Orcad and Cadence Software development–Developed C code; wrote batch files and visual basic scripts to automate processes; constructed python scripts for testing and troubleshooting Miscellaneous–Troubleshot hardware problems

Led undergraduate Physical Implementation VLSI lab with 60nm technology Explained protocols, assisted students, answered questions, graded homework

Verified CADD architectural layout Reviewed wiring diagrams Developed keyboard and mouse application macros

Developed VHDL code in Actel Libero SoC design suite Translated code from Verilog to VHDL Verified proper functionality of hardware using function generator and oscilloscope

Focus Area: Control Systems; Thesis - "A Model Order Reduction Method for Lightly Damped State Space Systems" - Used MATLAB to create computationally efficient model order reduction method for both continuous and discrete time SISO and MIMO systems based on modal-canonic form of state space model.

Mathematics Minor; Senior Design Project-Worked with multidisciplinary team to condition power generated by wind turbine to fast and trickle charge NiMH battery packs. Generated schematic with Orcad, chose components, prototyped hardware on a breadboard; Honors Engineering Program; Tau Beta Pi