Dipl.-Ing. Meritxell Cabezas López
Angestellt, Senior Solution Manager, ETAS GmbH
Stuttgart, Deutschland
Werdegang
Berufserfahrung von Meritxell Cabezas López
3 Jahre und 4 Monate, Juli 2017 - Okt. 2020
Technical Project Manager
Robert Bosch GmbH
++ Lead cross functional development team ++ Planning, prioritization and tracking system activities ++ Analysis of cost/benefit of feature selection ++ defect management & variant handling ++ work with key stakeholders in product management & executive teams to define strategy & requirements ++ work with several teams to deliver in synch with set timelines ++ communicate regularly with senior management on status, risks & change control
1 Jahr und 6 Monate, Jan. 2017 - Juni 2018
System Architect
Robert Bosch GmbH
++ Requirement engineering ++ Development & quality assurance including tools like FMEA, FTA, RCB... ++ Responsible for customer documentation ++ System & Sw development for automotive gateway ECUs ++ Definition of System architecture ++ Acquisition support for GW projects ++ Expert for system state machine (Network managment), automotive communication (CAN, LIN, FlexRay, Ethernet) & diagnostic (DoIP)
2 Jahre und 4 Monate, Okt. 2014 - Jan. 2017
Guest Lecturer
Baden-Württemberg Cooperative State University
Current Subject: Sensors and Data Processing Department/Faculty: Industrial Enginnering Lecture: Telecommunication Systems and Processor Architecture Department/Faculty: Electical Enginnering Lecture: Digital System Design Department/Faculty: Mechatronics
1 Jahr und 1 Monat, Dez. 2015 - Dez. 2016
Senior System Engineer
Nokia
System engineer & customer support: Management of investigations lines for KPI improvements Presentation of different approaches to improve the base station performance to customer & internal management LTE L1 and L2 feature implementation (C/C++, DSP, FPGA, Eclipse) Evaluation of field and lab data (Perl/Python) System simulations (Matlab/Simulink) Coordination of R&D and test engineer team
1 Jahr und 11 Monate, Feb. 2013 - Dez. 2014
R&D Engineer (Algorithm/SW Development)
Alcatel-Lucent
**Implementation, test and verification of algorithms, procedures and protocols in DSP and Matlab for the Physical Layer in LTE (Long Term Evolution) **Feasibility studies from customer requirements **Contact person and coordinator for analog, DSP-& FPGA-Design and system integration
2 Jahre und 1 Monat, Feb. 2011 - Feb. 2013
R&D Engineer (Algorithm/FPGA Design)
Alcatel-Lucent
++Development, test and verification of RF signal conditioning algorithms (dpd, iqec, cfr) for 2G, 3G, 4G and multistandar radio access technology. ++Data acquisition and processing for 3GPP compliance tests ++ Hardware validation ++Development of Matlab models for analog components based on data-sheet specifications ++FPGA and DSP specification
ASIC/FPGA development
4 Monate, Juni 2006 - Sep. 2006
Web page programmer and system administrator
Colegi oficial d'enginyers de Telecomunicació
Intership.
Ausbildung von Meritxell Cabezas López
8 Monate, Feb. 2007 - Sep. 2007
MIMO systems
Stuttgart Universität
5 Jahre und 2 Monate, Sep. 2002 - Okt. 2007
Telecommunications
Universitat Politècnica de Catalunya (UPC)
- Wireless communications - communication networks - digital signal processing
Sprachen
Englisch
Fließend
Deutsch
Fließend
Spanisch
Muttersprache
Französisch
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