Michael Kogan
Selbstständig, Digital ASIC Implementation and DFT Consultant, IC-Link (Freelancer)
Munich, Deutschland
Werdegang
Berufserfahrung von Michael Kogan
Bis heute 10 Jahre und 6 Monate, seit Jan. 2014
Digital ASIC Implementation and DFT Consultant
IC-Link (Freelancer)
Provide following services: - Layout (physical implementation) of digital IC: RTL to GDSII - Design for test solutions: setup of test concept, DFT insertion, test vector generation. - Ramp up of young engineer, start-up teams.
2 Jahre und 11 Monate, Feb. 2011 - Dez. 2013
ASIC/FPGA Engineer
MATIS Deutschland GmbH
Onsite support of a customer from Automotive, Airspace and Defence market. Synthesis, DFT, Place&Route VHDL and FPGA Design
1 Jahr und 3 Monate, Nov. 2009 - Jan. 2011
Hardware desiner
Siemens AG
• Design and implementation of Hardware Programmable Components for Medical devices such as Computer tomography. • VHDL coding from spec • RTL verification and optimization for Xilinx FPGA and CPLD technologies. • Formal Verification and RTL quality check. • Adaptation of an old code to new spec and technology requirement • Validation of FPGA and CPLD implementation in lab. • EDA tools: ISE of Xilinx, HDL-Designer of Modelsim, Conformal LEC of Cadence
9 Monate, Feb. 2009 - Okt. 2009
Digital ASIC Implementation and DFT Consultant
Freelancer
Provide following services: - Layout (physical implementation) of digital IC: RTL to GDSII - Design for test solutions: setup of test concept, DFT insertion, test vector generation. - Ramp up of young engineer, start-up teams. - FPGA design. - Sales representation.
4 Jahre und 9 Monate, Mai 2004 - Jan. 2009
Lead Service Application Engineer
Cadence Design Systems GmbH
• Project management: schedule and Statement of Work (SOW) definition and monitoring. • Technical lead of flat (one man), and hierarchical (multi engineers) designs. Work in international teams (3-6 engineers) with colleagues from Russia, Israel, China, India and Europe. • Physical implementation: RTL-synthesis trough Place and Route Layout implementation to Physical Verification and Tape-out to foundry of high-performance and ultra-low-power SOC devices at 180nm - 65nm technologies, for various customers
• Technical lead. • Layout of complex high speed (1 GHz) SOC designs with LVDS driver and receivers at LSI Logic 180nm technology, with Synopsys and LSI Logic tools, for a customer from Super Computer market in UK. • DFT service: scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation. • FPGA design with Xilinx SpartanII technology
1 Jahr und 2 Monate, Sep. 2000 - Okt. 2001
Senior ASIC Designer
AST Ltd.
• Technical lead. • Distributor of NEC and Chip Express ASIC vendors in Israel. • Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout. • VHDL coding from spec. for Telecommunication and Medicine clients. • ASIC to ASIC conversion from old to most recent ChipExpress technology • VHDL design for complex ASIC & FPGA designs. • Customer trainings, and flow setup.
3 Jahre, Okt. 1997 - Sep. 2000
ASIC Designer
AST Ltd
• Distributor of Chip Express ASIC vendors in Israel • Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout. • FPGA to ASIC conversion from Xilinx and Altera to ChipExpress technology. • VHDL design for complex ASIC & FPGA designs.
Ausbildung von Michael Kogan
2 Jahre und 1 Monat, Sep. 1995 - Sep. 1997
Electronic Engineering
Tel-Hai Colledge
Micro-Elektronik VHDL coding FPGA, CPLD design
Sprachen
Deutsch
Fließend
Englisch
Fließend
Russisch
Muttersprache
Hebräisch
Fließend
Ukrainisch
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