Ajaykrishna Ettiyil

Provided expertise on RTL Coding in Verilog HDL, RTL Verification, Floor Planning, Placement, Routing Processes, Clock Tree Synthesis and Timing Analysis. Proficient experience with Synopsys Prime Time, Synopsys Fusion Compiler, Synopsys Design Compiler, Tanner EDA Tools, TCL Scripting, Intel Quartus Prime, VC Spyglass, and Intel ModelSim.

The internship provided expertise on various Strategic Business Units like Security Services Group, Pneumatic Business Group

Developed UART model for Vega based SoC simulation as part of the internship program. Language used: System C

The internship provided expertise on Teamwork and Collaboration, Time Management and Leadership