Sergey Kiryushkin
Angestellt, IT engeneer, hdl designer, OAO "VNIIRT"
Moscow, Russische Föderation
Werdegang
Berufserfahrung von Sergey Kiryushkin
Bis heute 12 Jahre und 10 Monate, seit Sep. 2011
IT engeneer, hdl designer
OAO "VNIIRT"
Creation and verification a design on an Altera FPGA on Verilog language. Realization of DSP algoritm and control system for radar part. Working with optical interface, DDR3 ram, flash, rs-485, CAN interface. Second task. Development DVB-T2 modulator on FPGA. Creation LDPC, Time Interleaver, Frame BUilder, Scheduler Using EDA tools: Altera Quartus II; Mentor ModelsimSim, QuestaSim; Mathworks Matlab.
6 Jahre und 10 Monate, Nov. 2004 - Aug. 2011
engineer, VLSI designer
SRISA RAS (Science Research Institute System Investigation)
modeling cmos transistors (bsim3v3, bsimsoi). Post-production testing of microprocessors on the tester Agilent 93000. Designing microprocessor's modules on Verilog and synthesys: SRAM with OCP interface; DMA controller between DDR2 RAM, RapidIO Interface and Core; Elementary functions FPU (sin, cos, atan, log2, 2^x, 1/x, sqrt). EDA Tools: NC Verilog Cadence, Debussy, Maple, DC Synopsys, Virtuoso Cadence, Assura/Diva, Altium Designer, MS Office, Visio, Project, Autocad.
Ausbildung von Sergey Kiryushkin
5 Jahre und 7 Monate, Sep. 1999 - März 2005
microelectronics, microprocessor engineering
National Research Nuclear University (Moscow Engineering Physics Institute)
Master degree in Computer Science
Sprachen
Englisch
Gut
Deutsch
Grundlagen
Russisch
Muttersprache